1. Field of the Invention
The present invention relates to an oscillator used as a clock source oscillation circuit for an information processor or a communication processor and capable of supplying a signal used as a reference for desired frequencies.
2. Description of Related Art
For use in information processors such as computers or in communication apparatuses, an oscillator in which a piezoelectric resonator such as a quartz resonator is used as an oscillation source has been used as a clock source or the like. Each of processing sections forming an information processor is supplied with a clock signal or the like having a suitable frequency on the basis of a signal supplied from such an oscillator. FIG. 18 shows an example of a conventional oscillator using a PLL circuit. This oscillator 90 is arranged so as to be able to select one of a plurality of frequencies predetermined to be output, and to output a signal having the selected frequency. The oscillator 90 has a quartz resonator 1, an oscillation signal output section 10 which oscillates the quartz resonator 1 to output an oscillation signal xcfx861 having a resonant frequency fc of the quartz resonator 1, a programmable divider (reference divider: RD) 15 which divides (by M) the oscillation signal xcfx861 to generate a reference signal xcfx862 having a frequency fr, a PLL circuit 20 which operates by being supplied with this reference signal xcfx862, a programmable divider (output divider: OD) 30 which divides (by X) a multiplied signal xcfx863 output from the PLL circuit 20 and having a frequency fp to generate an output signal xcfx864 having a frequency fo, and a buffer 35 which amplifies and outputs the output signal xcfx864. The PLL circuit 20 has a phase comparator 21 which compares the phase of reference signal xcfx862 supplied from the RD 15 and the phase of a signal fed back from a voltage controlled oscillator (VCO) 23, a low-pass filter (LPF) 22 which cuts off high frequency components of an output of the phase comparator 21 and supplies the cut output to the VCO 23, and the VCO 23 that oscillates so that the phases of the two signals input to the phase comparator 21 coincide with each other. Further, a feedback divider (FD) 24 is provided in a feedback circuit of the PLL circuit. The frequency of an output of the VCO 23 is divided (by N) by the FD 24 to be fed back to the phase comparator 21. Consequently, in the PLL circuit 20, multiplied signal xcfx863 formed by multiplying the signal input to the phase comparator 21 by N is output from the VCO 23.
Each of the dividers (frequency dividers) 15, 24, and 30 used in this oscillator 90 is a programmable divider capable of dividing the frequency of the input signal by a set frequency dividing number. Accordingly, in the oscillator 90 shown in FIG. 18, combinations of frequency dividing numbers M, N, and X for the frequencies to be output are previously set in a memory 95, and one of the combinations of the frequency dividing numbers M, N, and X stored in the memory 95 can be selected by a decoder 96 connected to an external input 94. For example, if the oscillator 90 uses a quartz resonator 1 having a resonant frequency fc of 20 MHz, it can select and output one of sixteen different frequencies according to a combination of four external terminals S0, S1, S2, and S3.
Use of a PLL oscillator using such a programmable divider has enabled one oscillator to cover a plurality of frequencies, thus making it possible to provide an oscillator capable of operating as stably as conventional quartz oscillators in the period before a restricted appointed limit of delivery. Recently, however, various requirements have been posed for reference oscillation sources and there has been a need to prepare various types of oscillators even if the above-described PLL oscillator is used. Further, the speed of development of information processors or communication apparatuses have been remarkably accelerated and, therefore, a need for manufacturing oscillators of new specifications or frequencies in a short period has arisen. On the other hand, the operating accuracies of information processors and communication apparatuses have been improved, so that there is a need to also improve the frequency accuracy of signals output from oscillators.
It is therefore an object of the present invention to provide an oscillator which is capable of outputting an output signal that is stable and accurate in frequency in comparison with conventional PLL oscillators, which can be manufactured in a short period, and which can be supplied at a low cost.
In the conventional PLL circuit, as described above, a quartz resonator having a resonant frequency adjusted with a predetermined degree of accuracy is used and the resonant frequency is multiplied by a predetermined combination of frequency dividing numbers to obtain an output signal of an intended frequency. On the other hand, the inventors of the present invention have found that output signals of various frequencies required by users can be obtained by setting the frequency dividing numbers for dividers to suitable values independent of each other. That is, in an oscillator of the present invention, an output signal of a desired frequency can be obtained by enabling suitable setting of frequency dividing numbers for dividers even if the resonant frequency of a quartz resonator is not adjusted to an ideal value, and high-precision output signals adjusted to various frequencies required by users can be obtained regardless of whether or not they are to be output.
This will be described in more detail with reference to a model case shown in FIG. 1. In FIG. 1, frequencies fp of an output signal (multiplied signal) from a PLL circuit are plotted, frequencies fp being obtained by changing the value of frequency dividing number M for a reference divider RD step by step from 5 to 10 and by changing the value of frequency dividing number N for the FD of the PLL step by step between 1 to 30 with respect to each value of frequency dividing number M. It can be understood that, if the values of frequency dividing numbers M and N can be variably set independent of each other in this manner, various frequencies can be obtained from one resonant frequency fc, as described below. For example, when the frequency dividing number M is 10, frequencies fp of 0.1 fc and 0.2 fc can be obtained. As frequencies between these two frequencies, four frequencies of fc/9, fc/8, fc/7, and fc/6 can be obtained by suitably changing the frequency dividing numbers M and N. Thus, frequencies of the multiplied signal output from the PLL circuit can be set with very fine pitches by using one quartz resonator. It is apparent that the pitches with which frequencies can be set can be made finer by increasing the frequency dividing number M for the reference divider RD. Conversely, even if a quartz resonator whose resonant frequency fc is different from the ideal resonant frequency is employed, a multiplied signal of a desired frequency can also be obtained by suitably setting the frequency dividing numbers M and N.
Thus, the oscillator of the present invention is characterized by comprising a piezoelectric resonator such as a quartz resonator, an oscillation signal output section for oscillating the piezoelectric resonator to output an oscillation signal of a first frequency, a first programmable divider (reference divider: RD) for dividing the frequency of the oscillation signal by a first frequency dividing number (frequency dividing number M) to obtain a reference signal of a second frequency, a PLL circuit section capable of operating by using the reference signal input thereto to obtain a multiplied signal of a third frequency, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number (frequency dividing number N) for a second programmable divider (feedback divider: FD) provided in a feedback circuit, and a setting section capable of variably setting the first and second frequency dividing numbers (frequency dividing numbers M and N) to values independent of each other.
Further, a third programmable divider (output divider: OD) capable of dividing the frequency of the multiplied signal by a third frequency dividing number (frequency dividing number X) may be provided and the setting section may be arranged to variably set the third frequency dividing number (frequency dividing number X) to a value independent of the first and second frequency dividing numbers. In some case, this OD enables the frequency dividing number M for the RD to be set to a smaller number to set the frequency of the reference signal to a higher frequency, thereby preventing deterioration of jitter as described below as well as obtaining an output signal more stable in frequency.
As shown in FIG. 1, since integers are set as frequency dividing numbers M and N for frequency dividing with the programmable dividers, frequencies fp obtained by the PLL circuit are determined digitally (discretely) while the frequency dividing numbers M and N are suitably set. Therefore, it is possible that there is no combination of frequency dividing numbers M and N for setting the obtained frequency within tolerance limits about the desired frequency. Also, there is a frequency band G about a frequency corresponding to an integer multiple of the resonant frequency fc in which no frequency can be set with any setting of frequency dividing number M, N, or X changed variously as possible. If the maximum value of the frequency dividing number M is Mmax, the frequency band G is as defined by xc2x1fc/Mmax. The ranges of frequency bands G corresponding to ranges in which the frequency fp of the multiplied signal cannot be variably set for these reasons can be limitlessly restricted by increasing frequency dividing number M. However, if the frequency dividing number M is increased, the second frequency of the reference signal, i.e., the input signal to the PLL circuit section, becomes so low that the signal obtained by multiplying this input signal while performing phase comparison is liable to deteriorate in accuracy and stability. That is, deterioration of jitter occurs. Therefore, it is desirable to set the frequency dividing number M below such a value that considerable deterioration of jitter is avoided.
In the oscillator of the present invention, therefore, an adjustment circuit capable of finely adjusting the first frequency with respect to the resonant frequency of the piezoelectric resonator is provided in the oscillation signal output section to finely adjust the frequency of the oscillation signal, thereby ensuring that even a signal having a frequency which cannot be covered by only discrete setting of the combination of frequency dividing numbers M and N, or which falls into the frequency band in which no frequency can be set can be output from the oscillator. Moreover, since the frequency dividing number M is limited to a suitable value such that considerable deterioration of jitter cannot occur, an output signal having high frequency accuracy and high stability can be obtained from the oscillator of this embodiment. The amount of adjustment by the adjustment circuit can be set in the setting section together with the frequency dividing numbers M and N. By variably setting these values, any frequency required by a user can be output. Conversely, even if a quartz resonator not adjusted to an ideal resonant frequency is used, a signal of the desired frequency can be output. Thus, there is no need for frequency adjustment of the quartz resonator itself and the oscillator can be set to any frequency required by a user after it has been manufactured, thus facilitating mass-production of the oscillator. As a result, an oscillator capable of obtaining an output signal having a desired frequency with improved stability can be supplied in a very short period at a low cost.
As the adjustment circuit for finely adjusting the resonant frequency of the piezoelectric resonator in the oscillation signal output section, a circuit having a plurality of weighted capacitance arrays may be used. A circuit having a variable-capacitance diode is also available. Each of these circuits enables the adjustment amount to be set as a digital value and therefore enables the adjustment amount to be stored and set in the setting section together with the frequency dividing numbers M and N. To store these frequency dividing numbers M and N, frequency dividing number X, or the adjustment amount in the setting section, a ROM (read only memory) may be used. If a change with time, resetting after setting these values, and enabling the memory to be used with suitable set values for inspection are taken into consideration, it is desirable to use an EPROM, i.e., rewritable ROM, as the above-mentioned ROM. However, the oscillator may have the piezoelectric resonator, the oscillation signal output section, the first programmable divider, the PLL circuit section and the setting section packaged integrally with each other and covered with a mold resin. If the oscillator uses such packaging, the EPROM cannot be irradiated with ultraviolet rays. On the other hand, an EEPROM or the like may be used. In such a case, however, the control system becomes complicated and high-priced. In the oscillator of the present invention, therefore, the arrangement may be such that a plurality of ROMs are provided in the setting section to enable at least the first and second frequency dividing numbers (M and N) or the amount of adjustment to be set in each of the ROMs. Thus, an oscillator can be provided which is simple in structure and low-priced but capable of resetting frequency dividing number M or N, the adjustment amount or the like.
An input section for controlling the operating state of the oscillator may be provided and information designating a function controllable by the input section may be stored in this ROM.
Further, to enable the oscillator to be set so that an output signal of the desired frequency can be obtained after the piezoelectric resonator, the oscillation signal output section, the first programmable divider, the PLL circuit section and the setting section have been packaged integrally with each other, it is desirable that the resonant frequency, i.e., the first frequency of the oscillation signal not yet adjusted by the adjustment circuit, should be measurable. For such an effect, the frequency obtained by setting each of frequency dividing numbers M, N, and X to 1 may be measured. However, it is desirable to provide a bypass circuit for enabling direct measurement of the oscillation signal bypassing the first programmable divider and the PLL circuit section.
Most of frequencies required to be supplied by the oscillator are those based on 32.768 kHz for communication or 33.333 kHz for systematic uses. A rectangular AT cut quartz resonator manufactured to oscillate a fundamental wave at 25.1 MHz produces the base of frequencies for systematic uses when the frequency dividing number M is 753, and the base of communication frequencies within a range in which adjustment can be easily performed by an adjustment circuit of about 10 ppm when frequency dividing number M is 766. Further, this quartz resonator is a resonator which can be manufactured at a low cost, which is free from coupling with spurious vibration, and which has a high yield. Consequently, it can be understood that almost all of the frequencies can be covered by using a quartz resonator of 25.1 MHz.
To set a frequency in the oscillator of the present invention, a method may be used in which, on the basis of the unadjusted resonant frequency measured by using the above-mentioned bypass circuit or the like, the first and second frequency dividing numbers are set to such numbers that the third frequency of the multiplied signal is obtained as a frequency closest to the desired frequency. Then, fine adjustment is performed so that the third frequency becomes equal to the desired frequency. In this manner, the oscillator can be set so as to output a signal having the desired frequency without performing frequency adjustment of the piezoelectric resonator itself. Needless to say, if it is desirable to perform frequency dividing in the third programmable divider (OD), the third frequency may be set to a frequency by considering a frequency dividing number X.
Another method may also be used in which, with respect to the desired frequency, the first and second frequency dividing numbers with which an output signal having the closest third frequency can be obtained are previously calculated on the basis of the ideal resonant frequency of the piezoelectric resonator, and the first frequency is finely adjusted on the basis of the first and second frequency dividing numbers to such a value that the desired frequency is obtained.
Such oscillation frequency setting operations may be performed solely before the oscillator is mounted on a circuit board. Alternatively, setting operations may be performed after the oscillator has been mounted on a circuit board. Further, frequency setting operations can be performed before, after or simultaneously with the process for inspection using probes connected to the circuit board. If frequency setting operations are performed after mounting the oscillator on a circuit board, the oscillation frequency can be set by reflecting a subtle change in the state of the resonator or the like caused by mounting on the circuit board. If such setting operations are performed before, after or simultaneously with the inspection process, the operation process can also be shortened. In a case of a conventional oscillator in which an oscillation frequency is uniquely determined on the maker side is used, no frequency setting operations are performed on the user side. Similarly, with respect to the oscillator of the present invention, oscillation frequency setting may be performed as steps integral with the sequence of inspection operations. In this manner, the oscillator of the present invention capable of variably changing the oscillation frequency is assembled and frequency-adjusted by the same number of steps or the same procedure as that for conventional oscillators in which the oscillation frequency cannot be changed.